Driven Electronics & Communication Engineering student focused on VLSI design, embedded systems and hardware innovation. Actively building projects at the intersection of AI, FPGA/Verilog and real-world problem solving. President of the OPTICA Student Chapter, leading initiatives in deep tech, and passionate about developing defense-grade and socially impactful systems, including safety tech and autonomous platforms.
An RTL coding platform for Verilog and SystemVerilog, created for the growing demand for RTL design engineers. Designs compile and simulate with Icarus Verilog inside a security-hardened Docker sandbox, served by a FastAPI backend that returns VCD waveforms. Built for reliability and scale.
Tech: Verilog, SystemVerilog, Icarus Verilog, Python, FastAPI, Docker
Visit BITFLOWA chip system that helps with mobile security in times of mobile theft and battery drain. I designed the entire VLSI architecture using FSM concepts in Verilog, working across VLSI, IoT and web development.
Tech: Verilog, FSM design, VLSI, IoT, Web
Visit TRANA-TRACEA startup initiative creating better hardware for citizen safety. As a founding member I work with the team on multidisciplinary ideas and tech that common people need.
Tech: ESP32, Raspberry Pi, PCB design, C
Visit NAVIELLeading the OPTICA Student Chapter: technical events, workshops and knowledge sessions on photonics, optics and advanced technologies, plus initiatives that connect students with research and innovation.
Tech: Photonics, MATLAB, Cadence, Python
Visit OPTICA CHAPTERWon the Viksit Bharat speech competition at district level and went on to state-level participation.
Knowledge sessions organized by the OPTICA Student Chapter to grow engagement with photonics, optics and advanced technologies.
Many prizes in public speaking competitions at Aditya University.
Planning and executing E-Summit with the Entrepreneurship Development Cell, and expanding student participation and outreach.
Part of the core team running Creathon, a large-scale entrepreneurial event, supporting idea validation and pitching strategies.
Technical events and workshops connecting students with research and innovation opportunities.
Moments from VEDA, the student symposium at Aditya University.
Project Space showcase with the Technical Hub team at Aditya University.
BitFlow, an RTL coding platform for Verilog and SystemVerilog, is online. Try it out.
Joined NAVIEL as a founding member, a startup initiative building hardware for citizen safety.
A VLSI chip system for mobile security during theft and battery drain, with the architecture designed using FSMs in Verilog.